Inventor · Grenoble, FR

Laurent Clavelier

29Patents
7h-index
39Co-inventors
61Inventor score

Filing activity: Aug 11, 2006 → Jun 7, 2013

Most-cited inventions

PatentTitleAreaCited byStatus
US8183630B2 Circuit with transistors integrated in three dimensions and having a dynamically adjustable threshold voltage VT Electricity 252 Active
US8853785B2 Integrated circuit with electrostatically coupled MOS transistors and method for producing such an integrated circuit Electricity 179 Active
US7598145B2 Method for producing Si1-yGey based zones with different contents in Ge on a same substrate by condensation of germanium Electricity 49 Active
US8890111B2 Method for manufacturing a very-high-resolution screen using a nanowire-based emitting anisotropic conductive film Electricity 26 Active
US9106199B2 Acoustic wave device including a surface wave filter and a bulk wave filter, and method for making same Emerging Cross-Sectional Technologies 15 Active
US7906439B2 Method of fabricating a MEMS/NEMS electromechanical component Emerging Cross-Sectional Technologies 12 Active
US8766433B2 Electronic chip having channels through which a heat transport coolant can flow, electronic components and communication arm incorporating said chip Electricity 7 Active
US8288250B2 Method for transferring chips onto a substrate Electricity 6 Active
US7608491B2 Method for manufacturing a SOI substrate associating silicon based areas and GaAs based areas Emerging Cross-Sectional Technologies 5 Active
US8142593B2 Method of transferring a thin film onto a support Emerging Cross-Sectional Technologies 4 Active
US8178427B2 Epitaxial methods for reducing surface dislocation density in semiconductor materials Electricity 4 Active
US8318555B2 Method of producing a hybrid substrate having a continuous buried electrically insulating layer Electricity 4 Active
US7759175B2 Fabrication method of a mixed substrate and use of the substrate for producing circuits Electricity 3 Active
US7732282B2 Transistor of the I-MOS type comprising two independent gates and method of using such a transistor Electricity 3 Active
US8664084B2 Method for making a thin-film element Electricity 3 Active
US7993949B2 Heterogeneous substrate including a sacrificial layer, and a method of fabricating it Performing Operations; Transporting 3 Active
US7678635B2 Method of producing a transistor Electricity 2 Active
US8501589B2 Method in the microelectronics fields of forming a monocrystalline layer Electricity 2 Active
US7972971B2 Method for producing Si1-yGey based zones with different contents in Ge on a same substrate by condensation of germanium Electricity 2 Active
US8445122B2 Data storage medium and associated method Emerging Cross-Sectional Technologies 2 Active
US7763915B2 Three-dimensional integrated C-MOS circuit and method for producing same Electricity 2 Active
US7625811B2 Method for producing distinct first and second active semi-conducting zones and use thereof for fabricating C-MOS structures Electricity 1 Active
US8809964B2 Method of adjusting the threshold voltage of a transistor by a buried trapping layer Electricity 1 Active
US8841202B2 Method of producing a hybrid substrate by partial recrystallization of a mixed layer Electricity 1 Active
US7989327B2 Manufacturing method for a semi-conductor on insulator substrate comprising a localised Ge enriched step Electricity 1 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.