High bandwidth low-latency semaphore mapped protocol (SMP) for multi-core systems on chips
US7765351B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2007 |
| Grant date | Jul 27, 2010 |
| Priority date | — |
| Expiry date | Jan 11, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/167
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for dynamically managing movement of semaphore data within the system. The system includes, but is no limited to, a plurality of functional units communicating over the network, a memory device communication with the plurality of functional units over the network, and at least one semaphore storage unit communicating with the plurality of functional unites and the memory device over the network. The plurality of functional units include a plurality of functional unit memory locations. The memory device includes a plurality of memory device memory locations. The at least one semaphore storage unit includes a plurality of semaphore storage unit memory locations. The at least one semaphore storage unit controls dynamic movement of the semaphore data among the plurality of functional unit memory locations, the plurality of memory device memory locations, the plurality of semaphore storage unit memory locations, and any combinations therof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.