Methods of incorporating process-induced layout dimension changes into an integrated circuit simulation netlist
US7765498B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2007 |
| Grant date | Jul 27, 2010 |
| Priority date | — |
| Expiry date | Sep 13, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Computer-implemented methods of generating netlists for use in post-layout simulation procedures. A lookup table includes a predetermined set of features (e.g., transistors of specified sizes and shapes) supported by an integrated circuit (IC) fabrication process, with dimensions and process induced dimension variations being included for each feature. A netlist is extracted from an IC layout, the extracted netlist specifying circuit elements (e.g., transistors) implemented by the IC layout and interconnections between the circuit elements. A search pattern is run on the IC layout to identify features in the IC layout corresponding to features included in the lookup table. Circuit elements in the extracted netlist that correspond to the identified features are then modified using values from the lookup table, and the modified netlist is output. In some embodiments, the netlist extraction, search pattern, and netlist modification are all performed as a single netlist generation step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.