Method for lithography for optimizing process conditions
US7767385B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2006 |
| Grant date | Aug 3, 2010 |
| Priority date | — |
| Expiry date | Jun 1, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/2022
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method of lithography is disclosed, which allows for independent resist process optimization of two or more exposure steps that are performed on a single resist layer. By providing for a separate post-exposure bake after each resist exposure step, pattern resolution for each exposure can be optimized. The method can generally be used with different lithographic techniques, and is well-suited for hybrid lithography. It has been applied to the fabrication of a device, in which the active area and the gate levels are defined in separate mask levels using hybrid lithography with an e-beam source and a 248 nm source respectively. Conditions for post-exposure bakes after the two exposure steps are independently adjusted to provide for optimized results.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.