Methods of manufacturing a semiconductor device including CMOS transistor having different PMOS and NMOS gate electrode structures
US7767512B2 · kind B2 · utility
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12Claims
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Key dates
| Filing date | Jan 24, 2008 |
| Grant date | Aug 3, 2010 |
| Priority date | — |
| Expiry date | Jul 24, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0177
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method of manufacturing a semiconductor device, a gate insulation layer is formed on a substrate including a first channel of a first conductive type and a second channel of a second conductive type different from the first conductive type. A first conductive layer including a first metal is formed on the gate insulation layer, and a second conductive layer including a second metal different from the first metal is formed on the first conductive layer formed over the second channel. The second conductive layer is partially removed by a wet etching process to form a second conductive layer pattern over the second channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.