Dummy vias for damascene process
US7767570B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2006 |
| Grant date | Aug 3, 2010 |
| Priority date | — |
| Expiry date | Dec 18, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making an integrated circuit includes providing a low-k dielectric layer on a substrate, the low-k dielectric layer including or adjacent to a plurality of conductive features; patterning the low-k dielectric layer to form trenches; patterning the low-k dielectric layer to form conductive vias and dummy vias, wherein each of the conductive vias is aligned with at least one of the plurality of the conductive features and at least one of the trenches, and each of the dummy vias is a distance above the plurality of conductive features; filling the trenches, conductive vias, and dummy vias using one or more conductive materials; and planarizing the conductive material(s).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.