Vencent Chang
19Patents
5h-index
28Co-inventors
62Inventor score
Filing activity: May 15, 2001 → Jun 21, 2013
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7432042B2 | Immersion lithography process and mask layer structure applied in the same | Physics | 34 | Expired |
| US6458705B1 | Method for forming via-first dual damascene interconnect structure | Electricity | 23 | Expired |
| US6680252B2 | Method for planarizing barc layer in dual damascene process | Electricity | 13 | Expired |
| US7767570B2 | Dummy vias for damascene process | Electricity | 8 | Active |
| US7960821B2 | Dummy vias for damascene process | Electricity | 6 | Active |
| US7531399B2 | Semiconductor devices and methods with bilayer dielectrics | Electricity | 4 | Active |
| US7648918B2 | Method of pattern formation in semiconductor fabrication | Emerging Cross-Sectional Technologies | 3 | Active |
| US6844143B2 | Sandwich photoresist structure in photolithographic process | Emerging Cross-Sectional Technologies | 3 | Expired |
| US7642101B2 | Semiconductor device having in-chip critical dimension and focus patterns | Electricity | 3 | Active |
| US8119533B2 | Pattern formation in semiconductor fabrication | Emerging Cross-Sectional Technologies | 2 | Active |
| US8124323B2 | Method for patterning a photosensitive layer | Physics | 2 | Active |
| US7387969B2 | Top patterned hardmask and method for patterning | Electricity | 1 | Expired |
| US8394576B2 | Method for patterning a photosensitive layer | Physics | 1 | Active |
| US8384159B2 | Semiconductor devices and methods with bilayer dielectrics | Electricity | 0 | Active |
| US9091923B2 | Contrast enhancing exposure system and method for use in semiconductor fabrication | Physics | 0 | Active |
| US8815496B2 | Method for patterning a photosensitive layer | Physics | 0 | Active |
| US9366969B2 | Methodology for implementing enhanced optical lithography for hole patterning in semiconductor fabrication | Physics | 0 | Active |
| US8623231B2 | Method for etching an ultra thin film | Electricity | 0 | Active |
| US8472005B2 | Methodology for implementing enhanced optical lithography for hole patterning in semiconductor fabrication | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.