Patent · US Active

Forming robust solder interconnect structures by reducing effects of seed layer underetching

US7767575B2 · kind B2 · utility

0Cited by

11References

5Claims

0Family size

Assignee

Tessera Intellectual Properties, Inc. · US

Inventors

Kamalesh K. Srivastava · Wappingers Falls, US
Subhash L. Shinde · Croton-on-Hudson, US
Tien-Jen Cheng · Bedford, US
Sarah H. Knickerbocker · Hopewell Junction, US
Roger A. Quinn · Rhinebeck, US
William E. Sablinski · Beacon, US
Julie C. Biggs · Wappingers Falls, US
David E. Eichstadt · Chicago, US
Jonathan H. Griffith · Hopewell Junction, US

Key dates

Filing date	Jan 2, 2009
Grant date	Aug 3, 2010
Priority date	—
Expiry date	Jan 2, 2029

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02P80/30
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening of a first diameter, and a solder material is formed over the barrier layer using a second patterned opening of a second diameter. The second patterned opening is configured such that the second diameter is larger than the first diameter.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.