Patent · US Expired

Semiconductor component with integrated capacitance structure and method for fabrication thereof

US7768054B2 · kind B2 · utility

20Cited by

5References

29Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Thomas Benetik · Munich, DE
Erwin Ruderer · Borgo San Lazzaro, DE

Key dates

Filing date	Mar 24, 2003
Grant date	Aug 3, 2010
Priority date	—
Expiry date	May 30, 2024

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/0002
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A semiconductor component has an insulating layer which is formed on a semiconductor substrate and in which a capacitance structure (K) is formed. The capacitance structure (K) has at least two metallization planes (1 to 7) which are arranged parallel to one another and are each connected to an electrical connecting line. Arranged between the metallization planes (1 to 7) is at least one electrically conductive region (1a to 1j; 2a to 2j; 31a to 36a; 41a to 46a; 5a to 5f) for producing a capacitance surface, the electrically conductive region (1a to 1j; 2a to 2j; 31a to 36a; 41a to 46a; 5a to 5f) being electrically connected only to one of the metallization planes (1 to 7).

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.