Patent · US Active

Semiconductor die package including embedded flip chip

US7768108B2 · kind B2 · utility

11Cited by

62References

20Claims

0Family size

Assignee

FAIRCHILD SEMICONDUCTOR CORPORATION · US

Inventors

Yong Liu · Yichun City, CN
Jeff Ju · Gorham, US
Zhongfa Yuan · Suzhou, CN
Roger Luo · Shanghai, CN

Key dates

Filing date	Mar 12, 2008
Grant date	Aug 3, 2010
Priority date	—
Expiry date	Jul 19, 2028

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/18161
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A semiconductor die package. The semiconductor die package includes a leadframe structure, a first semiconductor die comprising a first surface attached to a first side of the leadframe structure, and a second semiconductor die attached to a second side of the leadframe structure. The second semiconductor die comprises an integrated circuit die. A housing material is formed over at least a portion of the leadframe structure, the first semiconductor die, and the second semiconductor die. An exterior surface of the molding material is substantially coplanar with the first surface of the semiconductor die.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.