Semiconductor memory device voltage generating circuit for avoiding leakage currents of parasitic diodes
US7768842B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2008 |
| Grant date | Aug 3, 2010 |
| Priority date | — |
| Expiry date | Jan 21, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4074
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A voltage generating circuit for semiconductor memory devices for use in avoiding the occurrence of leakage currents associated with parasitic diodes is presented. The circuit controls and stabilizes the generation of a fedback negative voltage to prevent parasitic diode malfunctions by a in a wordline driver. The voltage generating circuit includes a controller being fedback the negative voltage and detecting a potential difference between backbias voltage provided to a substrate of the cell and the negative voltage to generate a control signal. The voltage generating circuit also includes a voltage generator being fedback the negative voltage to detect a level thereof, and which subsequently generates and provides the negative voltage in response to the detected results of the negative voltage and the control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.