Flexible, low cost apparatus and method to introduce and check algorithm modifications in a non-volatile memory
US7769943B2 · kind B2 · utility
1Cited by
17References
5Claims
0Family size
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Key dates
| Filing date | Apr 4, 2007 |
| Grant date | Aug 3, 2010 |
| Priority date | — |
| Expiry date | Dec 11, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory includes input/output buffers, a memory array having memory cells coupled to the input/output buffers, and row and column decoders, and a voltage-generator circuit coupled to the row and column decoders. A microcontroller is coupled to the command user interface. Switch-instruction circuitry selectively provides instructions to the microcontroller from the read-only memory and from off chip through on-board t-latches coupled to the input/output buffers under control of a command user interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.