Multiple thread instruction fetch from different cache levels
US7769955B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2007 |
| Grant date | Aug 3, 2010 |
| Priority date | — |
| Expiry date | Dec 3, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0897
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing apparatus is provided wherein processing circuitry executes multiple program threads including at least one high priority thread and at least one lower priority thread. Instructions required by the threads are retrieved from a cache memory hierarchy comprising multiple cache levels. The cache memory hierarchy includes a bypass path for omitting a predetermined level of the cache memory hierarchy when performing a lookup procedure for a required instruction and for bypassing said predetermined level of the cache memory hierarchy when returning said required instruction to said processing circuitry. The bypass path is used by default when the requested instruction is for a lower priority thread.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.