Avoiding livelock using intervention messages in multiple core processors
US7769958B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2007 |
| Grant date | Aug 3, 2010 |
| Priority date | — |
| Expiry date | Mar 4, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1032
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Livelocks are prevented in multiple core processors by canceling data access requests upon determining that they conflict with other data access requests. A requesting processor core sends a data access request potentially causing livelock to a cache coherency manager. A cache coherency manager receives data access requests from multiple processor. The cache coherency manager sends intervention messages to all of the processor cores in response to all data access requests that may cause livelock. Upon receiving an intervention message from the cache coherency manager, the processor core determines if the intervention message corresponds with any of its own pending data access requests. If the intervention message is associated with a data access request conflicting with one of its own pending data access requests, the processor core responds to the invention message by directing the cache coherency manager to cancel its own conflicting pending data access request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.