Through substrate via semiconductor components
US7772123B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2008 |
| Grant date | Aug 10, 2010 |
| Priority date | — |
| Expiry date | Aug 19, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01079
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure and method of forming through substrate vias in forming semiconductor components are described. In one embodiment, the invention describes a method of forming the through substrate via by filling an opening with a first fill material and depositing a first insulating layer over the first fill material, the first insulating layer not being deposited on sidewalls of the fill material in the opening, wherein sidewalls of the first insulating layer form a gap over the opening. The method further includes forming a void by sealing the opening using a second insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.