Stacked semiconductor structure and fabrication method thereof
US7772685B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2006 |
| Grant date | Aug 10, 2010 |
| Priority date | — |
| Expiry date | Jan 28, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked semiconductor structure and fabrication method thereof are provided. The method includes mounting and connecting electrically a semiconductor chip to a first substrate, mounting on the first substrate a plurality of supporting members corresponding in position to a periphery of the semiconductor chip, mounting a second substrate having a first surface partially covered with a tape and a second surface opposite to the first surface on the supporting members via the second surface, connecting electrically the first and second substrates by bonding wires, forming on the first substrate an encapsulant for encapsulating the semiconductor chip, the supporting members, the second substrate, the bonding wires, and the tape with an exposed top surface, and removing the tape to expose the first surface of the second substrate and allow an electronic component to be mounted thereon. The present invention prevents reflow-induced contamination, spares a special mold, and eliminates flash.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.