Structure and method of mapping signal intensity to surface voltage for integrated circuit inspection
US7772866B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 7, 2007 |
| Grant date | Aug 10, 2010 |
| Priority date | — |
| Expiry date | May 19, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/34
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention provide a test structure for inspection of integrated circuits. The test structure may be fabricated on a semiconductor wafer together with one or more integrated circuits. The test structure may include a common reference point for voltage reference; a plurality of voltage dropping devices being connected to the common reference point; and a plurality of electron-collecting pads being connected, respectively, to a plurality of contact points of the plurality of voltage dropping devices. A brightness shown by the plurality of electron-collecting pads during an inspection of the integrated circuits may be associated with a pre-determined voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.