Test operation of multi-port memory device
US7773439B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2006 |
| Grant date | Aug 10, 2010 |
| Priority date | — |
| Expiry date | Jun 9, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/107
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-port memory device includes a plurality ports, a plurality of banks, a plurality of global data buses, first and second I/O controllers, and a test input/output (I/O) controller. The ports perform a serial I/O data transmission. The banks perform a parallel I/O data transmission with the ports. The global data buses are employed for transmitting data between the ports and the banks. The first I/O controller controls a serial data transmission between the ports and external devices. The second I/O controller controls a parallel data transmission between the ports and the global buses. The test I/O controller generates test commands based on a test command/address (C/A) inputted from the external devices and transmits a test I/O data with the global data bus during a test operation mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.