Strained channel transistor structure and method
US7776699B2 · kind B2 · utility
3Cited by
4References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2008 |
| Grant date | Aug 17, 2010 |
| Priority date | — |
| Expiry date | Mar 30, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A transistor device structure comprising: a substrate portion formed from a first material; and a source region, a drain region and a channel region formed in said substrate, the source and drain regions comprising a plurality of islands of a second material different from the first material, the islands being arranged to induce a strain in said channel region of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.