Patent · US Active

Process for through silicon via filing

US7776741B2 · kind B2 · utility

38Cited by

3References

30Claims

0Family size

Assignee

Novellus Systems, Inc. · US

Inventors

Jonathan D. Reid · Sherwood, US
Katie Qun Wang · Portland, US
Mark J. Willey · Portland, US

Key dates

Filing date	Aug 18, 2008
Grant date	Aug 17, 2010
Priority date	—
Expiry date	Sep 13, 2028

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/00014
WIPO fieldSurface technology, coating
WIPO sectorChemistry

Abstract

A semiconductor electroplating process deposits copper into the through silicon via hole to completely fill the through silicon via in a substantially void free is disclosed. The through silicon via may be more than about 3 micrometers in diameter and more that about 20 micrometers deep. High copper concentration and low acidity electroplating solution is used for deposition copper into the through silicon vias.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.