High bandwidth cache-to-processing unit communication in a multiple processor/cache system
US7777330B2 · kind B2 · utility
263Cited by
15References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 5, 2008 |
| Grant date | Aug 17, 2010 |
| Priority date | — |
| Expiry date | Nov 27, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A processor/cache assembly has a processor die coupled to a cache die. The processor die has a plurality of processor units arranged in an array. There is a plurality of processor sets of contact pads on the processor units, one processor set for each processor unit. Similarly, the cache die has a plurality of cache units arranged in an array. There is a plurality of cache sets of contact pads on the cache die, one cache set for each cache unit. Each cache set is in contact with one corresponding processor set.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.