Delay locked loop
US7777542B2 · kind B2 · utility
6Cited by
15References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 27, 2006 |
| Grant date | Aug 17, 2010 |
| Priority date | — |
| Expiry date | Feb 28, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0814
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a delay locked loop for achieving a delay locked state by correcting a phase difference between a reference clock and an internal delayed clock and for indicating the state that a larger delay amount than a maximum delay amount of a delay line is required, or a smaller delay amount than a minimum delay amount of delay line is required. A control unit resets the delay locked loop according to the state of the delay line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.