Erase operation control sequencing apparatus, systems, and methods
US7778086B2 · kind B2 · utility
31Cited by
4References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2007 |
| Grant date | Aug 17, 2010 |
| Priority date | — |
| Expiry date | Jul 16, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus, systems, and methods may operate to receive an external erase command at a control circuit coupled to an erasable memory array located on a substrate. A global select gate voltage may thereafter be enabled for application to wordline transistors coupled to the erasable memory array after a voltage applied to the substrate has reached a preselected initiation voltage level between about zero volts and an ultimate erase voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.