Method and apparatus for dynamically managing instruction buffer depths for non-predicted branches
US7779232B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2007 |
| Grant date | Aug 17, 2010 |
| Priority date | — |
| Expiry date | Sep 3, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3804
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for dynamically managing instruction buffer depths for non-predicted branches reduces wasted energy and resources associated with low confidence branch prediction conditions. A portion of the instruction buffer for a instruction thread is allocated for storing predicted branch instruction streams and another portion, which may be zero-sized during high prediction confidence conditions, is allocated to the non-predicted branch instruction stream. The size of the buffers is adjusted dynamically in conformity with an on-going prediction confidence that provides a measure of how well branch prediction mechanisms are working for a given instruction thread. An alternate instruction fetch address table can be maintained and multiplexed with the main fetch address register for addressing the instruction cache, so that the instruction stream can be quickly shifted to the non-predicted path when a branch instruction is resolved to the non-predicted path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.