Operation method of flash memory device capable of down-shifting a threshold voltage distribution of memory cells in a post-program verify operation
US7782681B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2007 |
| Grant date | Aug 24, 2010 |
| Priority date | — |
| Expiry date | Oct 29, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3454
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a driving method of a flash memory device including a selected first bit line and an unselected second bit line, a program voltage of a pulse is applied to word lines of all memory cells in a block passing an erase verify operation. After the first and second bit lines are precharged to a predetermined level, a ground voltage is applied to the word lines of all the memory cells in the block. The memory cells are evaluated for a predetermined time shorter than an evaluation time of a read operation. Whether or not a memory cell passing a verify operation exists among the memory cells is sensed. Resultantly, when the memory cell passing the verify operation exists, the memory cells in the block are programmed to a desired level using a predetermined program voltage and a step voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.