Dual stress memory technique method and related structure

US7785950B2 · kind B2 · utility

Assignees

• International Business Machines Corporation · US
• SAMSUNG ELECTRONICS CO., LTD. · KR
• Chartered Semiconductor Manufacturing LTD · SG

Inventors

• Sunfei Fang · Lagrangeville, US
• Jun Jung Kim · Seojong-myeon, KR
• Zhijiong Luo · Poughkeepsie, US
• Hung Y. Ng · New Milford, US
• Nivo Rovedo · Lagrangeville, US
• Young Way Teh · Singapore, SG

Key dates

• Filing date: Nov 10, 2005
• Grant date: Aug 31, 2010
• Expiry date: Apr 26, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0184

Abstract

A method for providing a dual stress memory technique in a semiconductor device including an nFET and a PFET and a related structure are disclosed. One embodiment of the method includes forming a tensile stress layer over the nFET and a compressive stress layer over the pFET, annealing to memorize stress in the semiconductor device and removing the stress layers. The compressive stress layer may include a high stress silicon nitride deposited using a high density plasma (HDP) deposition method. The annealing step may include using a temperature of approximately 400-1200° C. The high stress compressive silicon nitride and/or the anneal temperatures ensure that the compressive stress memorization is retained in the pFET.