Patent · US Active

Integrated circuit system with wafer trimming

US7786551B2 · kind B2 · utility

2Cited by
4References
17Claims
0Family size

Assignee

Inventors

Key dates

Filing dateSep 15, 2006
Grant dateAug 31, 2010
Priority date—
Expiry dateDec 27, 2026

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L21/302
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

An integrated circuit system includes an integrated circuit wafer, forming a trimmed edge on the integrated circuit wafer, and applying a thinning process on the integrated circuit wafer with the trimmed edge.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.