Hermetic seal and reliable bonding structures for 3D applications
US7786596B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2008 |
| Grant date | Aug 31, 2010 |
| Priority date | — |
| Expiry date | Jun 13, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A sealed microelectronic structure which provides mechanical stress endurance and includes at least two chips being electrically connected to a semiconductor structure at a plurality of locations. Each chip includes a continuous bonding material along it's perimeter and at least one support column connected to each of the chips positioned within the perimeter of each chip. Each support column extends outwardly such that when the at least two chips are positioned over one another the support columns are in mating relation to each other. A seal between the at least two chips results from the overlapping relation of the chip to one another such that the bonding material and support columns are in mating relation to each other. Thus, the seal is formed when the at least two chips are mated together, and results in a bonded chip structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.