Semiconductor memory device and erase method in the same
US7787299B2 · kind B2 · utility
5Cited by
0References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2008 |
| Grant date | Aug 31, 2010 |
| Priority date | — |
| Expiry date | Nov 27, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/344
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device and an erase method in the same are disclosed. The semiconductor memory device includes a memory cell array configured to have a cell string in which memory cells are coupled, a block switch configured to switch a global word line and a word line of the memory cell array, a block decoder configured to control the block switch, and a recycle switch configured to use an erase voltage charged in a P-well of the memory cell array as a supply voltage of the block decoder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.