Formation of metal silicide layer over copper interconnect for reliability enhancement

US7790617B2 · kind B2 · utility

Assignee

• Chartered Semiconductor Manufacturing LTD · SG

Inventors

• Yeow Kheng Lim · Singapore, SG
• Wei Lu · Singapore, SG
• Liang-Choo Hsia · Singapore, SG
• Jyoti Gupta · Singapore, SG
• Chim Seng Seet · Singapore, SG
• Hao Zhang · Beijing, CN

Key dates

• Filing date: Nov 12, 2005
• Grant date: Sep 7, 2010
• Expiry date: Apr 17, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76883
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of fabrication of a sputtered metal silicide layer over a copper interconnect. We form a dielectric layer over a conductive layer. We form an interconnect opening in the dielectric layer. We form a copper layer at least filling the interconnect opening. We planarize the copper layer to form a copper interconnect in the interconnect opening. The copper interconnect is over polished to form a depression. We form metal silicide layer over the copper interconnect using a low temperature sputtering process. We can form a cap layer over the metal silicide layer.