Memory cell having a buried phase change region and method for fabricating the same
US7791057B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 22, 2008 |
| Grant date | Sep 7, 2010 |
| Priority date | — |
| Expiry date | Sep 2, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/0004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory cells are described along with methods for manufacturing. A memory cell as described herein includes a bottom electrode comprising a base portion and a pillar portion on the base portion, the pillar portion having a width less than that of the base portion. A dielectric surrounds the bottom electrode and has a top surface. A memory element is overlying the bottom electrode and includes a recess portion extending from the top surface of the dielectric to contact the pillar portion of the bottom electrode, wherein the recess portion of the memory element has a width substantially equal to the width of the pillar portion of the bottom electrode. A top electrode is on the memory element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.