Method of increasing path coverage in transition test generation
US7793176B2 · kind B2 · utility
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4References
8Claims
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Key dates
| Filing date | Apr 5, 2007 |
| Grant date | Sep 7, 2010 |
| Priority date | — |
| Expiry date | Apr 23, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318328
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for automatically generating test patterns for digital logic circuitry using an automatic test pattern generation tool. The method includes generating test patterns and applying faulty behavior to various paths within the digital logic circuitry. As each circuit path is tested, tested circuit nodes along the circuit path are marked as “exercised.” Subsequent test paths are assembled by avoiding marked circuit nodes. In this manner, coverage of paths tested may be increased and many circuit nodes can be tested efficiently.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.