Methods for contact resistance reduction of advanced CMOS devices
US7795124B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2006 |
| Grant date | Sep 14, 2010 |
| Priority date | — |
| Expiry date | Apr 8, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for reducing contact resistance in semiconductor devices are provided in the present invention. In one embodiment, the method includes providing a substrate having semiconductor device formed thereon, wherein the device has source and drain regions and a gate structure formed therein, performing a silicidation process on the substrate by a thermal annealing process, and performing a laser anneal process on the substrate. In another embodiment, the method includes providing a substrate having implanted dopants, performing a silicidation process on the substrate by a thermal annealing process, and activating the dopants by a laser anneal process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.