Capacitor integrated in a structure surrounding a die
US7795615B2 · kind B2 · utility
13Cited by
12References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2005 |
| Grant date | Sep 14, 2010 |
| Priority date | — |
| Expiry date | Aug 1, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit comprises a chip including a circuit area surrounded by a peripheral area, the peripheral area extending to an edge of the chip. The integrated circuitry is disposed within the circuit area. No active circuit is disposed within the peripheral area. A barrier is disposed within the peripheral area and surrounds the circuit area. The barrier includes a capacitor structure integrated therein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.