Memory device having drift compensated read operation and associated method
US7796424B2 · kind B2 · utility
31Cited by
0References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2007 |
| Grant date | Sep 14, 2010 |
| Priority date | — |
| Expiry date | Apr 3, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes a memory array and a read control circuit configured to effectuate a read operation of a memory cell in the array. The read control circuit is configured so that the read operation contemplates one or more drift conditions associated with the memory cell. A method of reading a memory cell is also disclosed and includes detecting one or more drift conditions of a memory cell, and setting one or more read reference levels based on the one or more detected drift conditions. The memory cell is then read using the set one or more read reference levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.