Flash memory device and method of programming the same
US7796438B2 · kind B2 · utility
11Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2007 |
| Grant date | Sep 14, 2010 |
| Priority date | — |
| Expiry date | Dec 30, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory device may include a memory cell array, a page buffer unit, and a switching element. The page buffer unit may include first and second latches and is configured to program data into the memory cell array and read data from the memory cell array. The switching element enables the first latch during a verify operation of a first program based on a first verify voltage, and enables or disables the first latch in order to execute a verify operation of a second program based on a second verify voltage lower than the first verify voltage depending on whether data to be programmed has been stored in the second latch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.