Processor having parallel vector multiply and reduce operations with sequential semantics
US7797363B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2005 |
| Grant date | Sep 14, 2010 |
| Priority date | — |
| Expiry date | Sep 30, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/388
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor comprises a plurality of arithmetic units, an accumulator unit, and a reduction unit coupled between the plurality of arithmetic units and the accumulator unit. The reduction unit receives products of vector elements from the arithmetic units and a first accumulator value from the accumulator unit, and processes the products and the first accumulator value to generate a second accumulator value for delivery to the accumulator unit. The processor implements a plurality of vector multiply and reduce operations having guaranteed sequential semantics, that is, operations which guarantee that the computational result will be the same as that which would be produced using a corresponding sequence of individual instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.