Trench MOSFET and method of manufacture utilizing two masks
US7799642B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2007 |
| Grant date | Sep 21, 2010 |
| Priority date | — |
| Expiry date | Oct 26, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/662
Abstract
A method for manufacturing a trench MOSFET semiconductor device comprises: providing a heavily doped N+ silicon substrate; forming an N type epitaxial layer; forming a thick SiO2 layer; creating P body and source area formations by ion implantation without any masks; utilizing a first mask to define openings for a trench gate and a termination; thermally growing a gate oxide layer followed by formation of a thick poly-Silicon refill layer without a mask to define a gate bus area; forming sidewall spacers; forming P+ areas; removing the sidewall spacers; depositing tungsten to fill contacts and vias; depositing a first thin barrier metal layer; depositing a first thick metal layer; utilizing a second metal mask to open a gate bus area; forming second sidewall spacers; depositing a second thin barrier metal layer; depositing a second thick metal layer; and planarizing at least the second thick metal layer and the second thin metal layer to isolate the source metal portions from gate metal portions, whereby the trench MOSFET semiconductor device is manufactured utilizing only first and second masks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.