Method of forming a high-k gate dielectric layer
US7799669B2 · kind B2 · utility
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23Claims
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Key dates
| Filing date | Apr 27, 2007 |
| Grant date | Sep 21, 2010 |
| Priority date | — |
| Expiry date | Apr 27, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a semiconductor device. The method comprises forming a dielectric layer. Forming the dielectric layer includes depositing a silicon oxide layer on a semiconductor substrate, nitridating the silicon oxide layer to form a nitrided silicon oxide layer and incorporating lanthanide atoms into the nitrided silicon oxide layer to form a lanthanide silicon oxynitride layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.