Array of contactless non-volatile memory cells

US7800159B2 · kind B2 · utility

Assignee

• Silicon Storage Technology, Inc. · US

Inventors

• Yuniarto Widjaja · Cupertino, US
• Henry A. O'M'Mani · Milpitas, US
• Prateep Tuntasood · San Jose, US
• Bomy Chen · Cupertino, US

Key dates

• Filing date: Oct 24, 2007
• Grant date: Sep 21, 2010
• Expiry date: May 15, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/035

Abstract

A plurality of non-volatile memory cell units are arranged in rows and columns in a single crystalline semiconductor substrate of a first conductivity type. Each cell unit has a first region of a second conductivity type in the substrate along the planar surface, and a second region of the second conductivity, spaced apart from the first region, with a channel region therebetween. The channel region has a first portion adjacent to the first region, a third portion adjacent to the second region and a second portion therebetween. A first and second floating gates are over the first portion and third portion respectively and are insulated therefrom. A first and second control gates are over the first and second floating gates respectively and are capacitively coupled thereto. A first and second erase gates are over the first and second regions respectively and are insulated therefrom. A word line is over the second portion and is insulated therefrom. Electrical contacts to the array are made along the extremities of the array.