Integrated circuit with metal silicide regions
US7800226B2 · kind B2 · utility
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14References
3Claims
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Key dates
| Filing date | Jun 22, 2007 |
| Grant date | Sep 21, 2010 |
| Priority date | — |
| Expiry date | Aug 16, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a metal silicide region in a silicon region of a semiconductor substrate. The method comprises forming a metal layer over the silicon region, then in succession forming a titanium and a titanium nitride layer thereover. As the substrate is heated to form the silicide, the titanium getters silicon dioxide on the surface of the silicon region and the titanium nitride promotes the formation of a smooth surface at the interface between the silicide layer and the underlying silicon region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.