Circuitized substrate with internal stacked semiconductor chips, method of making same, electrical assembly utilizing same and information handling system utilizing same
US7800916B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 9, 2007 |
| Grant date | Sep 21, 2010 |
| Priority date | — |
| Expiry date | Jul 17, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49151
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A circuitized substrate assembly comprised of at least two circuitized substrates each including a thin dielectric layer and a conductive layer with a plurality of conductive members as part thereof, the conductive members of each substrate being electrically coupled to the conductive sites of a semiconductor chip. A dielectric layer is positioned between both substrates and the substrates are bonded together, such that the chips are internally located within the assembly and oriented in a stacked orientation. A method of making such an assembly is also provided, as is an electrical assembly utilizing same and an information handling system adapted for having such an electrical assembly as part thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.