Integrated circuit having a memory cell arrangement and method for reading a memory cell state using a plurality of partial readings

US7800943B2 · kind B2 · utility

Assignee

• Qimonda AG · DE

Inventors

• Roberto Ravasio · Dalmine, IT
• Detlev Richter · Unterhaching, DE
• Gert Koebernik · Unterhaching, DE
• Girolamo Gallo
• Mirko Reissmann · Radeberg, DE
• Ramirez Xavier Veredas · Munich, DE

Key dates

• Filing date: Jan 18, 2008
• Grant date: Sep 21, 2010
• Expiry date: Sep 17, 2028

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C2213/71
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Embodiments of the invention relate generally to an integrated circuit having a memory cell arrangement and a method for reading a memory cell state using a plurality of partial readings. In an embodiment of the invention, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include at least one memory cell, the memory cell being capable of storing a plurality of memory cell states being distinguishable by a predefined number of memory cell threshold values, and a controller configured to read a memory cell state of the at least one memory cell using a number of reference levels that is higher than the predefined number of memory cell threshold values, wherein the reading includes a first partial reading using a first set of a plurality of reference levels and a second partial reading using a second set of a plurality of reference levels, wherein the second set of a plurality of reference levels includes at least one reference level which is different from the reference levels of the first set of a plurality of reference levels.