Flash memory device and operating method thereof
US7800946B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2008 |
| Grant date | Sep 21, 2010 |
| Priority date | — |
| Expiry date | Sep 25, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory device includes a plurality of memory cell blocks, a control unit, a program speed calculation unit, a voltage generator and a block select unit. Each memory cell block includes a string having a drain select transistor, a plurality of memory cells, a novel cell and a source select transistor. The control unit generates a block select signal in response to an address signal and generates an operation control signal in response to a command signal. The program speed calculation unit decides a level of an initial program voltage based on threshold voltages detected after a program operation of the novel cells. The voltage generator generates operating voltages including the initial program voltage of the level according to the operation control signal. The block select unit transfers the operating voltages to a memory cell block corresponding to the block select signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.