Memory having self-timed bit line boost circuit and method therefor
US7800959B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2008 |
| Grant date | Sep 21, 2010 |
| Priority date | — |
| Expiry date | Jan 27, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory has an array of memory cells, column logic, a write driver, a voltage detector, and a bootstrap circuit. The array of memory cells is coupled to pairs of bit lines and word lines. The column logic is coupled to the array and is for coupling a selected pair of bit lines to a pair of data lines. The write driver is coupled to the pair of data lines. The voltage detector provides an initiate boost signal when a voltage of a first data line of the pair of data lines drops below a first level during the writing of the pair of data lines by the write driver. The bootstrap circuit reduces the voltage of the first data line in response to the boost enable signal. This is particularly beneficial when the number of memory cells on a bit line can vary significantly as in a compiler.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.