Hybrid ESD clamp
US7804670B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2005 |
| Grant date | Sep 28, 2010 |
| Priority date | — |
| Expiry date | Jul 19, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/393
Abstract
A circuit for protecting a semiconductor from electrostatic discharge events includes a Zener diode (21) in series with a resistor (22) between a power line HV VDD and a ground fine HV VSS. A gate of a DMOS device (23) is connected to a node between the diode and the resistor. The drain and source of the DMOS are connected between the power lines. During an ESD event, the gate voltage of the DMOS increases and the ESD current will be discharged through the DMOS to ground. When the current exceeds the capacity of the channel of the DMOS, a parasitic bipolar transistor or transistors associated with the DMOS device acts in a controlled snapback to discharge the current to ground. The use of a vertical DMOS (VDMOS) instead of a lateral DMOS (LDMOS), can reduce the area of the device and improve the protection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.