Semiconductor memory device with signal aligning circuit
US7804723B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2006 |
| Grant date | Sep 28, 2010 |
| Priority date | — |
| Expiry date | Jan 21, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/108
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A signal aligning circuit includes a plurality of pads receiving input signals in parallel 1 bit by 1 bit; a first transferring unit for transferring the input signals as first signals in synchronization with a first clock signal of an internal clock, and transferring the input signals as second signals in synchronization with a second clock signal of the internal clock; a second transferring unit for transferring the first signals in synchronization with the second clock signal of the internal clock; and an aligning unit for aligning the first and second signals transferred from the first and second transferring units and outputting the aligned signal as output signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.