Caching memory attribute indicators with cached memory data field
US7805588B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2005 |
| Grant date | Sep 28, 2010 |
| Priority date | — |
| Expiry date | Jun 24, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing system may include a memory configured to store data in a plurality of pages, a TLB, and a memory cache including a plurality of cache lines. Each page in the memory may include a plurality of lines of memory. The memory cache may permit, when a virtual address is presented to the cache, a matching cache line to be identified from the plurality of cache lines, the matching cache line having a matching address that matches the virtual address. The memory cache may be configured to permit one or more page attributes of a page located at the matching address to be retrieved from the memory cache and not from the TLB, by further storing in each one of the cache lines a page attribute of the line of data stored in the cache line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.