Split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing
US7808839B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2007 |
| Grant date | Oct 5, 2010 |
| Priority date | — |
| Expiry date | Dec 20, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type in the substrate with a second region of the second conductivity type in the substrate, spaced apart from the first region. A continuous first channel region is defined between the first region and the second region. A plurality of floating gates are spaced apart from one another with each positioned over a separate portion of the channel region. A plurality of control gates are provided with each associated with and adjacent to a floating gate. Each control gate has two portions: a first portion over a portion of the channel region and a second portion over the associated floating gate and capacitively coupled thereto.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.