Patent · US Active

Integrated circuit having a subordinate test interface

US7810004B2 · kind B2 · utility

4Cited by

4References

22Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Albrecht Mayer · Deisenhofen, DE
Harry Siebert · Germering, DE

Key dates

Filing date	Apr 5, 2007
Grant date	Oct 5, 2010
Priority date	—
Expiry date	Feb 22, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/3656
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An integrated circuit having a subordinate test interface and method for transmitting digital data is disclosed. The integrated circuit includes at least one test interface that is adapted to write and read data in and from a data memory, the at least one test interface includes, for transmitting and receiving data of different content categories, one signal line each for every content category. The integrated circuit further includes an interface module for receiving and transmitting data, and that the interface module is, via the signal lines, connected with the test interface for transmitting the data of the different content categories.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.